Sub-micron multi-level metallization is one of the key technologies for the next generation of ultra large-scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology including for example, vias and metal interconnect lines, are required to withstand both thermal and electrical stresses over an extended period of time in order to form reliable integrated circuits. Formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality of integrated circuits.
Copper and copper alloys have become the metal of choice for filling sub-micron, high aspect ratio interconnect features in multi-level integrated circuits. As circuit densities increase, the widths of vias, contacts, and interconnect lines have decreased to sub-micron dimensions, whereas the thickness of the dielectric layers, through the use low-k (low dielectric constant) materials, have decreased at a slower pace. Consequently, the aspect ratios for the features, i.e., their height divided by width, has increased thereby creating additional challenges in adequately filling the sub-micron features with, for example, copper metal.
As a result of these process limitations, electrochemical plating (ECP), also referred to as electrochemical deposition (ECD) is a preferable method for filling copper interconnect structures such as via openings and trench line openings formed in multi-level semiconductor devices. Typically, electroplating uses a suspension of positively charged ions of deposition material, for example metal ions, in contact with a negatively charged substrate, as a source of electrons, to plate out the metal ions by an electrochemical reduction reaction onto the charged substrate, for example, a semiconductor wafer.
Metal ECD in general is a well-known art and can be achieved by a variety of techniques. Common designs of cells for electroplating a metal on semiconductor wafers involve positioning the plating surface of the semiconductor wafer within an electrolyte solution in juxtaposition to an anode to allow an electrolyte flow to impinge on the plating surface. The plating surface (cathode) and anode form an electricat circuit powered by a power supply such that metal ions in the electrolyte solution are reduced and plated out by an electrochemical reaction onto the conductive portion of the plating surface.
The addition of metal dopants to the electrolyte solution has been proposed in the prior art to add the metal dopants to plated copper features, for example copper interconnect features. Metal dopants added in prior art processes have typically focused on the addition of layers of metal dopants, for example lining the opening of a copper filled damascene to improve a resistance to electromigration of the copper into adjacent dielectric layers. While the addition of metal dopants has included various deposition processes including ECD, prior art processes have typically been accomplished by controlling the deposition electrical current to form homogeneously doped copper features where such methods rely strongly on the metal dopant concentration in the electrolyte to achieve a desired dopant concentration in the plated copper.
Several problems are created by prior art ECD processes including the inability to achieve desired dopant concentrations of certain metal dopants as well as requiring careful monitoring and control of the metal dopant concentration in the electrolyte to achieve a desired doping concentration.
There is therefore a need in the integrated circuit manufacturing art for an improved ECD method of depositing copper as well as copper dopants to achieve better control over desired dopant concentrations as well as forming copper interconnect features with desired metal dopant concentration profiles to achieve improved structural stability including a resistance to electromigration and stress induced migration of the copper filled interconnect features.
It is therefore among the objects of the present invention to provide an improved ECD method of depositing copper as well as copper dopants to achieve better control over desired dopant concentrations as well as forming copper interconnect features with desired metal dopant concentration profiles to achieve improved structural stability including a resistance to electromigration and stress induced migration of the copper filled interconnect features.